1. Field of the Invention
The present application relates to a circuit board and a chip package structure having the circuit board. More particularly, the present application relates to a circuit board in which bump pitches are relatively small and a chip package structure having the circuit board.
2. Description of Related Art
With the advance of integrated circuits, chip packaging technologies are diversified little by little. On account of advantages of miniaturized chip package size and shortened signal transmission path, a flip chip interconnect technology has been extensively applied to the field of chip packaging.
Nonetheless, in the flip chip interconnect process, solder bumps used for bonding a chip to a chip carrier are apt to be squeezed by the chip and collapsed, which results in reduction of manufacturing yield. Hence, a controlled collapse chip connection (C4) technology has been proposed by the related art to deal with the problem of bump collapse.
According to the C4 technology, protruding pre-bumps are formed on a chip carrier for connecting solder bumps of a chip. A method of forming the pre-bumps is described below. First, a seed layer is entirely formed on the chip carrier, and a patterned photoresist layer is formed on the seed layer. Here, the seed layer covers a solder resist layer and pads that are exposed by openings of the solder resist layer. Besides, the patterned photoresist layer has a plurality of openings respectively connecting the openings of the solder resist layer on the chip carrier. Note that the openings of the solder resist layer expose the pads. Next, by electroplating the seed layer, the openings of the solder resist layer and the openings of the patterned photoresist layer are filled with metal, so as to form the pre-bumps.
The aforesaid pre-bumps can support the solder bumps melted in the flip chip interconnect process, and therefore the conventional melted solder bumps squeezed by the chip can be prevented from being collapsed.
However, in the above-mentioned process of forming the pre-bumps, the openings of the patterned photoresist layer need to be connected to the openings of the solder resist layer, and the openings of the solder resist layer are completely exposed. Thus, the requirement for alignment accuracy poses a limitation on formation of the openings of the patterned photoresist layer. Thereby, a width of the openings of the patterned photoresist layer is greater than a width of the openings of the solder resist layer. As such, the width of the openings of the patterned photoresist layer cannot be reduced, and neither can dimensions and bump pitches of the pre-bumps and the solder bumps. Moreover, since the bump pitches are unlikely to be shortened, pitches among the chip pads on the chips cannot be correspondingly shortened.